1. Field of the Invention
The present invention relates to an integrated circuit apparatus, and more particularly to an impedance updating apparatus for a termination circuit.
2. Description of the Related Art
As speed of data transmission in and through data transmission systems increases, on-chip termination is required in integrated circuits of the system. FIG. 1 shows a conventional termination circuit for transmitting data in high speed. As shown, an output driver 1 is coupled to a-termination circuit 3 through a data line 2. If the termination circuit 3 as a receiver is connected to parallel termination through the data line 2 when the output driver 1 is a source termination, data in full swing can be transmitted and received, but the swing is reduced at the terminator circuit.
The termination circuit 3 includes transistors which behave as parallel impedance. Since in a memory device, a clock signal, an address signal, and a control signal are transmitted in a single direction, the termination circuit 3 should be continuously turned-on during chip operation. The characteristic impedance of the terminator circuit 3 may vary with variations in process parameters such as process, voltage and temperature (hereinafter referred to as PVT variation). For proper signal termination, the characteristic impedance of the termination circuit 3 should be kept constant.
Referring to FIG. 2a, which is a waveform illustrating an operation of a termination circuit in an on-transition state. The transistors in the terminator circuit are turned on during region xe2x80x98axe2x80x99 and region xe2x80x98bxe2x80x99, which are indicated with a logic symbol xe2x80x98111111xe2x80x99, wherein the xe2x80x98highxe2x80x99 signal is instantaneously bounced up and the xe2x80x98lowxe2x80x99 signal is instantaneously bounced down during transition as shown in xe2x80x98exe2x80x99 and xe2x80x98fxe2x80x99 of FIG. 3a, respectively. Then the bounced signal is again reflected into the output driver 1 (such as a transmitter circuit) in FIG. 1 and causes signal distortion.
Referring to FIG. 2b, which is a waveform illustrating an operation of a termination circuit in an off-transition state. If all the transistors are turned off as shown in xe2x80x98Cxe2x80x99 in the region xe2x80x98cxe2x80x99 or xe2x80x98Dxe2x80x99 in the region xe2x80x98dxe2x80x99 which are indicated as logic symbol xe2x80x9800000xe2x80x99, since the termination circuit is instantaneously in a very low state of impedance, the xe2x80x98highxe2x80x99 signal is instantaneously bounced down or the xe2x80x98lowxe2x80x99 signal is instantaneously bounced up during transition as shown in xe2x80x98gxe2x80x99 and xe2x80x98hxe2x80x99 of FIG. 3b, respectively. Then the bounced signal is again reflected into the output driver 1 (such as a transmitter circuit) in FIG. 1 and causes signal distortion.
Accordingly, a problem of the conventional termination circuit is system noise created due to the repeated on/off operations of the transistors, resulting from tracking and updating operations in response to variations in operation environment of chips or an internal PVT.
An impedance updating apparatus is provided which comprises: a terminator circuit for receiving and terminating an external input signal, the terminator circuit having an up-terminator and a down-terminator; and an update controller for separately controlling the up-terminator and the down-terminator based on the level of the external input signal.
According to an aspect of the invention, the update controller includes at least one latch for latching impedance codes of a programmable impedance controller, the impedance codes being used for controlling transistors in the up-terminator and down-terminator. The update controller performs updating impedance of the up-terminator, or down-terminator when an up-update enable signal or a down-update enable signal and a level of the external input signal correspond to a predetermined condition. And the update controller performs updating impedance of the up-terminator, or down-terminator in response to a level of the external input signal during set-up or hold time only.
An impedance updating termination circuit is provided which comprises: separate update controllers having a first inverter and a second inverter receiving an external input signal, a first latch connected to an output of the first inverter to store impedance information from a programmable impedance up controller, and a second latch connected to an output of the second inverter to store impedance information from a programmable impedance down controller, wherein the separate controller output an impedance update control signal of an up-terminator when the external input signal is a logic xe2x80x9chighxe2x80x9d, and output an impedance update control signal of an down-terminator when the external input signal is a logic xe2x80x9clowxe2x80x9d; and a terminator circuit having an up-terminator and a down-terminator connected to a common external input signal, wherein the terminator circuit receives impedance information from the first latch to update impedance of the up-terminator when a control signal for controlling an impedance update of the up-terminator is input from the separate update controller, and receives impedance information from the second latch to update impedance of the down-terminator when a control signal for controlling an impedance update of the down-terminator is input from the separate update controller.
The separate update controller further includes: a first NAND gate which receives at a first input the output of the first inverter and at a second input an up-update enable signal, the output of the first NAND gate being connected to the first latch; and a second NAND gate which receives at a first input the output of the second inverter and at a second input an up-update enable signal, the output of the second NAND gate being connected to the second latch, wherein the update controller generates a control signal for controlling up-update or down-update only when the level of the external input signal and the up-update enable signal or down-update enable signal are NANDed.
An impedance updating termination circuit is provided which comprises: a receiver circuit to receive an external input signal; a separate update controller having: an inverter connected to a second latch; an input buffer connected to an output of the receiver circuit at its input and to an internal clock signal determining set-up time or hold time, and the output of the buffer connected to a first latch at its out put and connected to the inverter at its output; a first latch for storing impedance information from a programmable impedance up controller; and the second latch for storing impedance information from a programmable impedance down controller, wherein the separate controller generates an up-update or down-update control signal in response to an up level or down level of an external input signal that passed through the receiver circuit to thereby control separately an up- or down-update of impedance; and a terminator circuit having an up-terminator and a down-terminator connected to a common external input signal from the transmitter circuit, wherein the terminator circuit receives impedance information from the first latch to update impedance of the up-terminator when a control signal for controlling an impedance update of the up-terminator is input from the separate update controller, and receives impedance information from the second latch to update impedance of the down-terminator when a control signal for controlling an impedance update of the down-terminator is input from the separate update controller.
The separate update controller further comprises: a first NAND gate connected to the output of the input buffer at its input and to an up-update enable signal that is periodically generated at its other input and connected to the first latch at its output; and a second NAND gate connected to the output of the input buffer at its input and an down-update enable signal being generated periodically at its other input and connected to the second latch at its output, wherein the update controller generates a control signal for controlling up-update or down-update when the level of the external input signal and the up-update enable signal or down-update enable signal are NANDed or ANDed.
An impedance updating method of termination circuit having up/down terminators and a separate update controller for detecting terminator through which minimum current flows in response to level of an external input signal is also provided which comprises the steps of: determining signal levels of an external input signal to thereby detect a terminator through which minimum current flows between the up or down terminator; and impedance updating the detected terminator through which minimum current flows.
According to the aspect of the invention, the step of determining is performed during set-up time or hold time and the step of determining is performed when a periodic update enable signal is present.